Example embodiments relate to a semiconductor memory device, for example, to a flash memory device and a method of verifying the same.
FIGS. 4a and 4b are timing diagrams illustrating one suspend during a program operation of a conventional memory, for example, flash memory. FIG. 4a illustrates a case where a verify operation is not performed after programming. FIG. 4b illustrates a case where a verify operation is performed after programming. FIGS. 4a and 4b are based on an operation mode in which a verify operation is not performed before programming. Referring to FIG. 4a, program operations for memory cells corresponding to addresses A0 to A3 sequentially proceed. However, when a suspend occurs during a program operation of a memory cell corresponding to an address A4, the program operation terminates. The program operation starts again from the point of when the program operation terminated, and the program operation is performed on the memory cell of the address A4. Then, program operation proceeds to an address A5, and a program operation is performed on a memory cell of the address A5.
Referring to FIG. 4b, program operations for memory cells corresponding to addresses A0 to A3 are sequentially performed and then respective verify operations are performed. When a suspend occurs during a program operation for a memory cell corresponding to an address A4, the program operation terminates. The program operation starts again from the point of when the program operation terminated, and then a verify operation is performed on the memory cell of the address A4. If it is determined that rewrite is unnecessary by using the verify operation, program operation proceeds to an address A5, and then a program operation is performed on a memory cell corresponding to the address A5.
According to the above description, a voltage stress is again applied to a memory cell of the same address by a program operation after resuming the program operation like all cases of FIGS. 4a and 4b. 
FIGS. 5a and 5b are timing diagrams illustrating a plurality of suspends during a program operation of a conventional memory, for example, flash memory. FIG. 5a illustrates a case where a verify operation is not performed after programming. FIG. 5b illustrates a case where a verify operation is performed after programming. FIGS. 5a and 5b are based on an operation mode in which a verify operation is not performed before programming. Referring to FIG. 5a, a program operation for memory cells corresponding to addresses A0 to A3 sequentially proceeds. However, when a suspend occurs during a program operation for a memory cell corresponding to an address A4, the program operation terminates. The program operation starts again from the point of when the program operation terminated, and the program operation is again performed on the memory cell of the address A4. However, a suspend occurs again in the memory cell corresponding to the address A4 during the resumed program operation, such that these operations repeat several times. When the suspend terminates finally, a program operation is performed on a memory cell corresponding to the address A4 again, and then program operation proceeds to an address A5. Then, a program operation is performed on a memory cell of the address A5.
Referring to FIG. 5b, a program operation for memory cells corresponding to addresses A0 to A3 is performed and then a verify operation is performed. When a suspend occurs during a program operation for a memory cell corresponding to an address A4, the program operation terminates. The program operation starts again from the point of when the program operation terminates, and then a verify operation is performed on the memory cell of the address A4. If it is determined that rewrite is unnecessary through the verify operation, program operation proceeds to an address A5, and then a program operation is performed on a memory cell corresponding to the address A5. A voltage stress is again applied to a memory cell of the same address by means of a plurality of program operations after resuming the program operation like all cases of FIGS. 4a and 4b. 
In a case of FIGS. 5a and 5b, a plurality of suspends during program operations continuously occur without one verify operation, such that voltage stresses of a plurality of program operations accumulate in a memory cell. Accordingly, this may cause voltage overstress in a memory cell. In a case of FIGS. 4a and 4b, voltage stress by a program operation, which is applied to a memory cell of the address A4, increases by one, but a plurality of voltage stresses accumulates for a long time as illustrated in FIGS. 5a and 5b. 